The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly relates to a semiconductor device having an interconnect structure including air gaps and a method for fabricating the semiconductor device.
In recent years, in order to increase the operation speed of semiconductor devices, application of an air gap interconnect structure to semiconductor device fabrication processes has been examined. Normally, for RC delays (i.e., delays generated from resistive components and capacitive components) of an interconnect, a delay generated from capacitive components is determined by a relative permittivity of an insulation film located around the interconnect. One reason why application of an air gap interconnect is put under examination now is that as the size of semiconductor devices has been reduced more and more, causes for delay due to a relative permittivity of an insulation film come to have as large influences as or even larger influences than influences of the operation speed of a transistor.
To cope with this, further reduction in relative permittivity of an insulation film has been examined as a possible solution. The relative permittivity of silicon oxide, which is mainly used as an interlevel insulation film, is 4.1. A low permittivity film (i.e., a porous low-k film) having a relative permittivity of about 2.0 has been recently developed. However, there is a limit to reduction in relative permittivity of a low permittivity film. In the air gap interconnect structure, gaps are formed around interconnects and thus the relative permittivity can be reduced to 1. Accordingly, the operation speed of the semiconductor device can be further increased. Therefore, practical application of air gap interconnects particularly in a 32 nm-interconnect width generation and beyond is expected.
As a method for forming air gaps according to a first known example, the following method is described in Japanese Laid-Open Publication No. 09-237831. First, a carbon layer is formed on an insulation film. Subsequently, interconnect grooves are formed in the carbon layer and then a metal film is buried in the interconnect grooves, thereby forming interconnects. Next, a silicon oxide film is deposited over an entire surface of the carbon layer as well as the interconnects. Subsequently, the carbon layer is ashed by heat treatment, thereby forming gaps between the interconnects. Then, formation of an interconnect layer is repeated, thereby forming multilayer interconnects. The above-described formation method is also described in Japanese Laid-Open Publication No. 2003-115534.
However, the method for forming an air gap interconnect structure according to the first known example has a problem that a silicon oxide film is supported by only interconnects and thus a mechanical strength of a semiconductor device is reduced. There also another problem arises that when misalignment between lower layer interconnects and contact holes for connecting the lower layer interconnects to upper layer interconnects caused in forming multilayer interconnects becomes out of an allowable range, the contact holes pass through to air gaps formed between the lower layer interconnects. As a solution to the above-described problems, an interconnect structure including nano-column air gaps has been proposed. In this structure, since nano-scale, column (pillar) shape air gaps are formed between interconnects, a high occupancy of insulation films between interconnects can be achieved, thus resulting in ensured mechanical strength. Moreover, even when misalignment between contact holes and lower layer interconnects is caused, the width of each of air gaps formed between lower layer interconnects is nano-scale and therefore the misalignment does not cause any problem.
Hereafter, a method for fabricating a semiconductor device using nano-column air gaps according to a second known example will be described with reference to FIGS. 6A and 6B.
FIGS. 6A and 6B are cross-sectional views illustrating respective steps for fabricating a copper interconnect having nano-column air gaps according to the second known example in order.
First, as shown in FIG. 6A, an interlevel insulation film 111 is formed on a semiconductor substrate (not shown) in which function devices and the like are formed. Subsequently, lithography is performed to form lower layer interconnect grooves 111a in the interlevel insulation film 111. Then, a barrier metal film 112a of a stacked layer film of tantalum (Ta) and tantalum nitride (TaN) and lower layer interconnects 112 of a copper film 112b are formed in the lower layer interconnect grooves 111a. 
Next, as shown in FIG. 6B, a hole resist pattern 113 including openings each having a diameter of several ten nano-meters is formed on the interlevel insulation film 111 including the lower layer interconnects 112 by lithography.
Next, using the hole resist pattern 113 as a mask, dry etching is performed to the interlevel insulation film 111, thereby forming a plurality of nano column holes in the interlevel insulation film 111.
However, the fabrication method according to the second known example has three problems as described below. First, as in FIG. 6B, it is difficult to form a pattern with a size of 50 nm or smaller using the present lithography technique. Therefore, in forming nano holes each having a diameter of 50 nm or smaller, some other method has to be used.
Second, the hole resist pattern 113 is formed on the lower layer interconnects (metal) 112 and the interlevel insulation film 111, which are made of different materials, for example, having different reflectivities, respectively. Accordingly, a light exposure amount in lithography on metal differs from that on an insulation film. As a result, it becomes difficult to form a uniform hole resist pattern 113 and shapes of resultant nano holes are non-uniform.
Third, in forming nano holes in the interlevel insulation film 111, the lower layer interconnects 112 are also subjected to a severe reactive ion etching process by dry etching. Therefore, it becomes difficult to form highly reliable interconnects.
To solve above-described problems, as a third known example, the following structure is adopted in Japanese Laid-Open Publication No. 2005-268783. FIG. 7 is a cross-sectional view illustrating a semiconductor device to which a structure including nano-column air gaps described in Japanese Laid-Open Publication No. 2005-268783 is applied. First, to solve the second problem, lower layer interconnect grooves 121a are formed in an interlevel insulation film 121 formed on a semiconductor substrate 120. Thereafter, another insulation film is evenly formed on the interlevel insulation film in which the lower layer interconnect grooves 121a are formed. As a result, a uniform hole pattern can be formed.
Moreover, to solve the third problem, as shown in FIG. 7, for example, holes 121b and another insulation film are formed so that the holes 121b are located in part between the lower layer interconnect grooves 121a. Subsequently, after said another insulation film is removed, oxide film sidewalls 123 are formed to serve as a protective film for protecting the lower layer interconnect grooves 121a and the interlevel insulation film 121. Lastly, a barrier film 122a and a metal film 122b are buried in the lower layer interconnect grooves 121a, thereby forming lower layer interconnects 122. As a result, the lower layer interconnects 122 are no longer subjected to an ion etching process.
However, use of the method for fabricating a semiconductor device according to the third known example can not solve the first problem that formation of a resist pattern having a size of 50 nm or smaller using the current lithography technique is difficult, and also causes another problem. Specifically, there arises a problem that because the oxide film sidewalls 123 are formed on each of side walls of the interlevel insulation film 121, the lower layer interconnect 122 and the like, an effective permittivity between the lower layer interconnects 122 is increased and variation in interconnect width are increased.